The present invention relates to a semiconductor device used in a semiconductor integrated circuit and a manufacturing method thereof, and more particularly concerns a semiconductor device which is provided with a bonding pad formed above an active region on a surface of a semiconductor substrate and a manufacturing method thereof.
There is a tendency in a semiconductor integrated circuit that its integration level (the number of semiconductor elements integrated on a chip) has been increased and its chip size has become larger, in accordance with the progress in manufacturing an electronic device with higher functions and performance which is equipped with semiconductor integrated circuits. On the other hand, in response to the need for a smaller package containing a semiconductor integrated circuit, a chip has been downsized by reducing the processing size (reducing the design rule) and by miniaturizing the package containing the semiconductor integrated circuit.
A semiconductor integrated circuit chip can be roughly divided into two regions: one is an operation region (also referred to as an active region in some cases) inside the chip, and the other is a bonding pad region formed on a surface of the chip. The operation region includes a region on which semiconductor elements such as a transistor, etc. are provided (an active region), and a region of metal wiring connecting the semiconductor elements (a wiring region). The bonding pad region is a region on which bonding pads are formed. A bonding pad is an electrode for electrical connection to an external section by, for example, wire bonding using a fine gold wire, for the input/output of a signal to/from the semiconductor integrated circuit and for other purposes. Generally, the bonding pads are provided on the perimeter of a chip, avoiding a region overlying the active region of a semiconductor substrate. This is to prevent stress caused at the bonding pad when carrying out bonding such as wire bonding due to mechanical pressure, etc. applied to the bonding pad, from being applied to the action region constituting the semiconductor element. In general, the bonding pad is a rectangle in which the length of one side is about 50 xcexcm to 100 xcexcm, and a plurality of the bonding pads are placed on the perimeter of the chip at intervals about 10 xcexcm to 20 xcexcm.
Formerly, it was enough to provide one layer of metal wiring for connecting semiconductor elements on a semiconductor integrated circuit chip. However, in accordance with the development in functions and performance and the increase in the integration level, the wiring has become longer and complicated, causing defects such that a signal cannot be transmitted correctly. To solve such a problem, a multilayer wiring structure, in which a plurality of wiring layers are laminated via inter-layer insulation films, has been proposed. This structure increase flexibility and facilitates the improvement in the function and performance of semiconductor integrated circuits, and the improvement of their integration level.
Meanwhile, as semiconductor integrated circuits come to have higher functions and performance, the number of terminals used for input/output, etc. increases accordingly, reaching several hundreds to nearly one thousand. Since one bonding pad is required for one terminal, the number of bonding pads required also increases in response to the increase in the number of terminals, and several hundreds to nearly one thousand bonding pads are required. Along with such an increase in the number of bonding pads, the area of the bonding region on a chip surface is increasing. Therefore, chip size reduction in a semiconductor integrated circuit (miniaturization of a semiconductor integrated circuit) cannot be achieved, failing to satisfy the need for the miniaturization of an electronic device equipped with a semiconductor integrated circuit.
As a method for chip size reduction, a method has been proposed in which a bonding pad, conventionally provided on the perimeter of a chip to avoid a region overlying an active region of a semiconductor substrate, is provided in an region overlying an active region of a semiconductor substrate (above the active region). (Hereinafter, a bonding pad provided in a region overlying an active region of a semiconductor substrate is referred to as an area pad.)
First, referring to FIG. 8, an example for forming an area pad in a semiconductor device with a two-layer wiring structure disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989 (Tokukaihei 1-91439, published on Apr. 11, 1989) [Japanese Patent No. 2694252] will be described.
As shown in FIG. 8, a first Al wiring layer 102 is formed on a Si substrate (semiconductor substrate) 101. On the first Al wiring layer 102, inter-layer insulation films 103 to 105 (a plasma nitride film 103, an NSG 104, and a PSG 105) are provided, then a through hole is formed through the inter-layer insulation films 103 to 105 by means of patterning and etching. A second Al wiring layer 106 is formed on the inter-layer insulation films 103 to 105, and a final passivation film 107 is formed on the second Al wiring layer 106.
On the final passivation film 107, an opening section (pad opening section) 110 is formed above an active region (not shown). With this structure, an electrode pad is formed above the active region.
Therefore, in the foregoing semiconductor device, it can be considered that an exposed section 106a in the second Al wiring layer 106 (the part at the opening section 110) functions as an electrode pad formed above the active region, that is, as an area pad.
Next, referring to FIG. 9, an example for forming a bonding pad in a semiconductor device with a three-layer wiring structure disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992 (Tokukaihei 4-62855, published on Feb. 27, 1992) will be described.
A first wiring layer 203 is formed on a silicon substrate 201 on which an element (not shown) is provided, via an insulation film 202. A second wiring layer 209 is formed on the first wiring layer 203 via inter-layer insulation films 205 to 207 (an insulation film 205, a glass-coated film 206, and an insulation film 207). A third wiring layer 215 is formed on the second wiring layer 209 via inter-layer insulation films 212 to 214. The third wiring layer 215 is connected with the second wiring layer 209 via through holes formed at predetermined positions in the inter-layer insulation films 212 to 214. A protection film 210 is formed on the third wiring layer 215.
Further, to relieve stress during wire bonding, a section 203a of the first wiring layer 203, which is a section underlying a bonding pad section 215a (a section below the bonding pad section 215a), is processed to have a virtually same shape with that of the bonding pad section 215a. 
In the foregoing semiconductor device, the process for forming the bonding pad section 215a is completed by forming a hole 211 for bonding in the protection film 210. Therefore, it can be considered that an exposed section in the third wiring layer 215 (the part at the hole 211 for bonding) becomes the bonding pad section 215a for electrically connecting the semiconductor device to an external section.
Further, a section 209a of the second wiring layer 209, which is a section underlying the bonding pad section 215a (a section below the bonding pad section 215a), is divided into a plurality of parts by the inter-layer insulation films 212 to 214. Therefore, in the structure disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992, it can be considered that, in the second wiring layer 209, there are a plurality of wires of the section 209a, which is the section underlying the bonding pad section 215a, in a region underlying the bonding pad section 215a. 
Next, referring to FIG. 10, an example for forming an area pad in a semiconductor device with a two-layer wiring structure disclosed in Japanese Unexamined Patent Publication No. 5-251573/1993 (Tokukaihei 5-251573, published on Sep. 28, 1993) will be described.
As shown in FIG. 10, a base 302 and an emitter 303 are formed on a collector (silicon substrate) 301, and on the base 302 and the emitter 303, a first aluminum wiring 306 is formed via a silicon oxide film 304 and an silicon nitride film 305.
On the first aluminum wiring 306, inter-layer insulation films 307 to 309 are laminated, on which a second aluminum wiring 310 is formed. A section 310a of the second aluminum wiring 310 is used as a bonding pad for bonding a bonding wire 311. This bonding pad is located above the base 302, serving as an area pad.
The inter-layer insulation films 307 to 309 have a laminated structure in which a polyimide film 308 is sandwiched between plasma silicon films 307 and 309, so as to prevent the inter-layer insulation films from being cracked due to the stress during bonding.
However, in the conventional technique disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989, the second Al wiring layer 106 is used not only as wiring for electrically connecting to the wiring of the first Al wiring layer 102, but also as an area pad. Therefore, when using the second Al wiring layer 106 to form wiring between the semiconductor elements which should be insulated from the area pad, the wiring has to be formed so as to be bypassed around the area pad, in such a manner to avoid the area pad.
A semiconductor device shown in FIGS. 11A and 11B is also known as a conventional technique similar to that disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989. FIG. 11A is a schematic plan view showing an area pad having a gold bump and wiring formed in proximity to the area pad, and FIG. 11B is a sectional view taken along a line X-Xxe2x80x2 of FIG. 11A. In FIG. 11A, an inter-layer insulation film and a surface protection film are omitted, and only the area pads, the wiring, and the opening sections in the surface protection film are shown for easier understanding of the state of the wiring.
As shown in FIGS. 11A and 11B, a second wiring layer 403, which is made of a metal, is formed on a first wiring layer 401, made of a metal, via an inter-layer insulation film 402. On the second wiring layer 403, a surface protection film 404 having an opening section 404a is formed, and via the opening section 404a, a gold (Au) bump 405 is joined to a part of the second wiring layer 403. In this case, the part of the second wiring layer 403 joined to the gold bump 405 and the gold bump 405 are used as an area pad. The first wiring layer 401 has a plurality of wires 401a in a region below the gold bump 405, which are the wires for connecting a semiconductor element to an external section.
Although not shown, a semiconductor substrate having an active region (a region in which a semiconductor element is formed) is provided below the first wiring layer 401, that is, below the gold bump 405.
In this structure, in the connection between the second wiring layer 403 and the gold bump 405, the second wiring layer 403 below the gold bump 405 is formed so as to have virtually the same size (cross-sectional area) with that of the gold bump 405, which serves as an area pad, and the opening section 404a in the surface protection film 404 located between the second wiring layer 403 and the gold bump 405 is also formed so as to have virtually the same size (cross-sectional area) with that of the gold bump 405. Thus, in the second wiring layer 403, there is only one wire joined with the gold bump 405 in a region below the gold bump 405. Therefore, wires 403a connecting semiconductor elements, which should be insulated from the gold bump 405 (the two wires shown in the lower part of FIG. 11B), are subject to limitations on installed location, and as shown in FIG. 11A, they have to be formed so as to be bypassed around regions underlying the gold bump 405, in such a manner to avoid the regions. Thus, there is a need to reserve a wiring region for the bypassed wires 403a of the second wiring layer 403 in an area outside the region below the gold bump 405, requiring extra space for the wiring region on a chip. As a result, the effect of chip size reduction given by an area pad is lessened.
The gold bump 405 is generally formed such that its surface facing the second wiring layer 403 is a rectangle in which the length of one side is around 50 xcexcm to 100 xcexcm. On the other hand, the width of a wire is generally not more than 1 xcexcm. Thus, if the gold bump 405 is provided just above the active region of the semiconductor element, approximately 10 to 20 wires should be bypassed. As the number of the gold bump 405 increases, limitations on wiring become severer and more complicated, and the location for forming the gold bump 405 is also more limited.
These problems also occur in the conventional technique disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989. Therefore, in the structure disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989, there is a possibility that the effect given by an area pad cannot be fully utilized in practical use.
Besides, in the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992, although the position of an active region on the silicon substrate 201 is not clear, even if the active region on the silicon substrate 201 is supposed to be placed at a position underlying the bonding pad, that is, the semiconductor device is supposed to be structured to have an area pad, there is a following problem.
Specifically, in the structure disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992, the plurality of wires of the section 209a of the second wiring layer 209, the section underlying the bonding pad section 215a, are all electrically connected to the bonding pad section 215a. 
Consequently, the plurality of wires of the section 209a of the second wiring layer 209, the section underlying the bonding pad section 215a, can be used only as the wires to be connected to the bonding pad section 215a. Therefore, the plurality of wires of the section 209a which underlies the bonding pad section 215a cannot be used as the wires between semiconductor elements which should be insulated from the bonding pad section 215a. 
Besides, also in the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 5-251573/1993, a part of the second aluminum wiring 310 is used as an area pad, as in the case of the conventional technique disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989. Thus, it is impossible to place the wiring between semiconductor elements which should be insulated from an area pad, just below the area pad. Therefore, it is required that the wiring between semiconductor elements formed by the second aluminum wiring 310, which should be insulated from the area pad, is placed so as to be bypassed to avoid a region below the area pad.
FIGS. 12A and 12B show an example of a conventional technique which can solve the problem. FIG. 12A is a schematic plan view showing an area pad having a gold bump and wiring formed in proximity to the area pad, and FIG. 12B is a sectional view taken along a line Y-Yxe2x80x2 of FIG. 12A. In FIG. 12A, a first inter-layer insulation film, a second inter-layer insulation film, and a surface protection film are omitted, and only the area pads, the wiring, and the opening sections in the surface protection film are shown for easier understanding of the state of the wiring.
As shown in FIGS. 12A and 12B, a second wiring layer 503, which is made of a metal, is formed on a first wiring layer 501, made of a metal, via a first inter-layer insulation film 502. On the second wiring layer 503, a second inter-layer insulation film 504 is provided, in which a via hole 504a for electrical connection is formed. On the second inter-layer insulation film 504, a third wiring layer 505 is formed by metal deposition processing. Further, on the third wiring layer 505, a surface protection film 506 having an opening section 506a is formed, and via the opening section 506a, a gold (Au) bump 507 is joined to a part of the third wiring layer 505. In this case, the part of the third wiring layer 505 joined to the gold bump 507 and the gold bump 507 are used as an area pad.
Although not shown, a semiconductor substrate having an active region (a region in which a semiconductor element is formed) is provided below the gold bump 507, that is, below the first wiring layer 501. The second wiring layer 503 and the third wiring layer 505 are connected via the via hole 504a formed in the second inter-layer insulation film 504 in an area outside a region underlying the gold bump 507.
Further, in this structure, the third wiring layer 505 below the gold bump 507 is formed so as to have virtually the same size (cross-sectional area) with that of the gold bump 507, and the opening section 506a in the surface protection film 506 located between the gold bump 507 and the third wiring layer 505 is also formed so as to have virtually the same size (cross-sectional area) with that of the gold bump 507.
According to the structure shown in FIGS. 12A and 12B, it is possible to place a plurality of wires of the second wiring layer 503 in the region below the gold bump 507.
However, in the foregoing structure, the second inter-layer insulation film 504 and the third wiring layer 505 are further required, in addition to the structure shown in FIGS. 11A and 11B. Thus, in the process for manufacturing the semiconductor device shown in FIGS. 12A and 12B, it is required to add a process for depositing and processing the second inter-layer insulation film 504 and a process for depositing and processing the third wiring layer 505, to the process for manufacturing the semiconductor device shown in FIGS. 11A and 11B. Especially, it is required to add a photolithography process and an etching process, resulting in a decline in manufacturing efficiency and an increase in chip cost.
The present invention relates to a semiconductor device used in a semiconductor integrated circuit, etc., which includes a bonding pad located in a region overlying an active region of a semiconductor element (above the active region) and made up of a gold bump, etc., and a plurality of wires, and its object is to provide a semiconductor device which can simplify a manufacturing process, reduce the device""s size (chip size), improve the flexibility in the position for placing the bonding pad and the flexibility in providing wiring between semiconductor elements, and a manufacturing method for such a semiconductor device.
To achieve the foregoing object, a semiconductor device in accordance with the present invention is characterized by including:
a semiconductor substrate having an active region where a semiconductor element is formed;
a first wiring layer formed on the semiconductor substrate and electrically connected with the active region;
a second wiring layer formed on the first wiring layer via an inter-layer insulation film; and
a bonding pad for electrical connection with an external section, at least a part of which is formed so as to overlie the active region,
wherein the second wiring layer has a plurality of wires in a region underlying the bonding pad, in which a part of the wires is joined to the bonding pad, and other wires are insulated from the bonding pad by an insulation film formed between the other wires and the bonding pad.
According to the foregoing structure, a plurality of wires can be provided in the region underlying the bonding pad, where only one wire can be provided in the semiconductor device with a two-layer structure having a conventional area pad as shown in FIGS. 8, 10, 11A and 11B. Among the plurality of wires, the wires except that joined to the bonding pad are insulated from the bonding pad by the insulation film.
With this structure, it becomes possible to provide wires which should be insulated from the bonding pad, which are bypassed to avoid a region below the bonding pad in the semiconductor device with a two-layer structure having a conventional area pad, in the region underlying the bonding pad (in the region below the bonding pad) For example, when the bonding pad is provided in a region overlying an active region (a region above an active region) of each of three adjacent semiconductor elements in a semiconductor integrated circuit, a second wire connecting the semiconductor elements at the both ends can be provided in a region underlying the bonding pad in the middle. Thus, since there is no need to bypass wires, the area of the wiring region can be reduced, and chip size reduction can be achieved.
Further, there is no need in this structure to design wiring between semiconductor elements, etc. considering the position of the bonding pad, or, on the contrary, to specify the position of the bonding pad considering the wiring between the semiconductor elements, etc., which enhances the flexibility in providing the wiring between the semiconductor elements, etc. as well as the flexibility in the location of the bonding pad.
Besides, compared with the conventional semiconductor device in which the bonding pad is provided on the perimeter of a chip, where no wires are provided, so as to avoid an active region, considering the position of the wires between the semiconductor elements, etc., there is no need in this structure to provide a region exclusive for the bonding pad on the perimeter of a chip (a region where no wires are provided). Therefore, compared with the conventional semiconductor device, the area of the wiring region can be reduced, and chip size reduction can be achieved in the foregoing structure.
Furthermore, compared with the semiconductor device with a three-layer structure having the conventional area pad as shown in FIGS. 12A and 12B, the bonding pad can be directly joined to the second wiring layer without a third wiring layer in between in the foregoing structure, which eliminates the need for the third wiring layer and a protection film covering the third wiring layer. Therefore, processes for manufacturing the third wiring layer and the protection film covering the third wiring layer can be omitted, and the manufacturing process can be shortened. Consequently, production efficiency can be improved and manufacturing cost can be reduced.
Therefore, according to the foregoing structure, productivity improvement and cost reduction can be achieved, the device can be downsized, and the flexibility in providing the wiring between semiconductor elements, etc. and in the location of the bonding pad can be enhanced.
Incidentally, the wordings xe2x80x9coverliexe2x80x9d and xe2x80x9cunderliexe2x80x9d mean that an orthogonal projection of a section projected on a semiconductor substrate matches that of another section projected on the same semiconductor substrate.
To achieve the foregoing object, a method for manufacturing a semiconductor device in accordance with the present invention is characterized by including the steps of:
forming a semiconductor element on a semiconductor substrate;
forming a first wiring layer so as to be partially joined to the semiconductor element;
forming an inter-layer insulation film having a via hole, on the first wiring layer;
forming a second wiring layer on the inter-layer insulation film and in the via hole;
forming an insulation film on the second wiring layer;
forming an opening section in the insulation film; and
forming a bonding pad for electrical connection with an external section, by forming a metal film on the insulation film and in the opening section,
wherein a plurality of wires are formed in the step of forming the second wiring layer;
the insulation film is formed so as to cover the plurality of wires in the step of forming the insulation film;
the opening section is formed so as to expose only a part of the plurality of wires covered with the insulation film, in the step of forming the opening section; and
the bonding pad is formed so as to at least partially overlie the semiconductor element, and to overlie at least one of the wires covered with the insulation film, in the step of forming the bonding pad.
According to the foregoing method, a semiconductor device in which a plurality of wires are provided in a region underlying the bonding pad, where only one wire can be provided in a semiconductor device with a two-layer structure having a conventional area pad, can be obtained. Among the plurality of wires, those except the wire joined to the bonding pad is covered with the insulation film, so they are insulated from the bonding pad.
With this method, wires to be insulated from the bonding pad can be placed in the region underlying the bonding pad (the region below the bonding pad). Thus, since there is no need to bypass the wires, the area of the wiring region can be reduced, and chip size reduction can be achieved. Further, the flexibility in providing the wiring between the semiconductor elements, etc. and the flexibility in the location of the bonding pad can be enhanced.
Compared with the conventional semiconductor device in which the bonding pad is provided on the perimeter of a chip, where no wires are provided, so as to avoid an active region, considering the position of the wires between the semiconductor elements, etc., the area of the wiring region can be reduced, and chip size reduction can be achieved by the foregoing method.
Furthermore, according to the foregoing method, the bonding pad can be directly joined to the second wiring layer without a third wiring layer in between, which eliminates the need for the third wiring layer and a protection film covering the third wiring layer. Therefore, processes for manufacturing the third wiring layer and the protection film covering the third wiring layer can be omitted, and the manufacturing process can be shortened. Consequently, production efficiency can be improved and manufacturing cost can be reduced.
Therefore, according to the foregoing method, productivity improvement and cost reduction can be achieved, the device can be downsized, and the flexibility in providing the wiring between semiconductor elements, etc. and in the location of the bonding pad can be enhanced.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.